by Eriemon · Codex Skill · ★ 161
English | 中文 Verilog Generator A Codex-ready agent skill for disciplined Verilog-2001 RTL workflows. Verilog Generator turns an AI coding agent into a more reliable RTL engineering assistant. It provides trigger metadata, workflow instructions, interface templates, deterministic runtime helpers, examples, and validation gates for moving from confirmed hardware intent to synthesizable Verilog and self-checking testbenches. This repository is primarily an agent skill package.
| Stars | 161 |
| Forks | 44 |
| Language | Python |
| Category | Codex Skill |
| License | Apache-2.0 |
| Quality Score | 56.392/100 |
| Last Updated | 2026-05-22 |
| Created | 2026-05-08 |
| Platforms | codex, python |
| Est. Tokens | ~32k |
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verilog-generator is Agent skill for Verilog-2001 RTL generation and FPGA design workflows.. It is categorized as a Codex Skill with 161 GitHub stars.
verilog-generator is primarily written in Python. It covers topics such as agent-skill, codex-skill, eda.
You can find installation instructions and usage details in the verilog-generator GitHub repository at github.com/Eriemon/verilog-generator. The project has 161 stars and 44 forks, indicating an active community.
verilog-generator is released under the Apache-2.0 license, making it free to use and modify according to the license terms.